8.1 ARM Cortex-M0+ core
The ARM Cortex-M0+ core runs at an operating frequency of up to 30 MHz using a
two-stage pipeline. Integrated in the core are the NVIC and Serial Wire Debug with four
breakpoints and two watchpoints. The ARM Cortex-M0+ core supports a single-cycle I/O
enabled port for fast GPIO access.
The core includes a single-cycle multiplier and a system tick timer.
8.2 On-chip flash program memory
The LPC81xM contain up to 16 kB of on-chip flash program memory. The flash memory
supports a 64 Byte page size with page write and erase.
8.3 On-chip SRAM
The LPC81xM contain a total of up to 4 kB on-chip static RAM data memory.
8.4 On-chip ROM
The 8 kB on-chip ROM contains the boot loader and the following Application
Programming Interfaces (API):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
• Power profiles for configuring power consumption and PLL settings
• USART driver API routines
• I2C-bus driver API routines
8.5 Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The
tight coupling to the CPU allows for low interrupt latency and efficient processing of late
arriving interrupts.
8.5.1 Features
• Controls system exceptions and peripheral interrupts.
• On the LPC81xM, the NVIC supports 32 vectored interrupts including up to 8 external
interrupt inputs selectable from all GPIO pins.
• Four programmable interrupt priority levels with hardware priority level masking.
• Software interrupt generation using the ARM exceptions SVCall and PendSV.
• Relocatable interrupt vector table using vector table offset register.
8.5.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags. Individual interrupt flags may also represent more than one interrupt
source
